System Building Basics

How to calculate bandwidth
For this example, let's use a tile that is a 320 pixels wide by 320 pixel tall.  The input will be 50hz / 12 bit using 1x stream. Below are a few key stats we know and will use for the calculation.  I am also referencing a page of the HELIOS User Guide (Output Port Capacity table).
  • Panel Pixel Count: 320 x 320 pixels (102,400 total pixels)  
  • Panel Ethernet Speed: 1G
  • Panel Max Streams: 2
  • Pixels per switch port: 510,000 (looking at the 10 bit / 1G column and the 50hz row)
  • Pixels per switch: 510,000 (1G link) x 10 (fiber link is 10G) = 5,100,000
  • Pixels per HELIOS: 5.1m (switch total) x 8 (# of fiber outputs) = 40,800,000

Using the above data, we need to make sure that we don't exceed capacity at each of those steps.  So the total panels you can do at each stage are as follows:
  • Switch Port: 510,000 / 102,400 = 4.98 => 4 panels per port 
  • Total per switch: 5.1 million / 102,400 (or just multiple 4 x 10) = 49.8 => 49 panels
  • Total per HELIOS: 40.8 million / 102,400 (or just multiple by 8) = 398.4 => 398 panels
10 bit - Doing the exercise again but instead setting HELIOS to 10-bit requires the same calculations but using the pixel capacity numbers from the 10-bit column instead.  You can do 5 panels (5.95 panels) per switch port and 59 per total switch. 

Camera+/GhostFrame Multisource 

Remembering that the above are the capacities for a single stream, now we need to account for multiple.  The fastest way of doing that is to take that Panel Pixel Count # (102,400 pixels) and multiply it by the number of streams.  For example, 2 streams would be 204,800 pixels per panel. Once you have that number, redo the math above using the new pixel count. 

Low Latency 

There are 2 options for using Low Latency (Tile and Processor).  They are very different and need to be accounted for when designing system. 

  • Tile Low Latency - There are no capacity/mapping implications when using Tile Low Latency.  All tiles "should" be capable of doing it which assumes they are tuned correctly.   
  • Processor Low Latency - This latency feature requires a good bit of consideration when requested.  The basic rules are that the wall needs to be wired in vertical columns and stacked ports likely need to be interleaved (the key rules can be found in the HELIOS User Guide).  It is highly recommended that you reach out to support@megapixelvr.com and let us help validate your Low Latency build.   


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